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Texas Instruments /MSP432P401R /ITM /ITM_TCR

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Interpret as ITM_TCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ITMENA)ITMENA 0 (TSENA)TSENA 0 (SYNCENA)SYNCENA 0 (DWTENA)DWTENA 0 (SWOENA)SWOENA 0 (en_0b00)TSPRESCALE 0ATBID0 (BUSY)BUSY

TSPRESCALE=en_0b00

Description

ITM Trace Control Register

Fields

ITMENA

Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.
TSENA

Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle.
SYNCENA

Enables sync packets for TPIU.
DWTENA

Enables the DWT stimulus.
SWOENA

Enables asynchronous clocking of the timestamp counter.
TSPRESCALE

TSPrescale Timestamp prescaler.

0 (en_0b00): no prescaling

1 (en_0b01): divide by 4

2 (en_0b10): divide by 16

3 (en_0b11): divide by 64
ATBID

ATB ID for CoreSight system.
BUSY

Set when ITM events present and being drained.

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data